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| www..com Data Sheet VT6212 / VT6212L PCI USB 2.0 Controller Revision 1.06 December 7, 2005 VIA TECHNOLOGIES, INC. www..com Copyright Notice: Copyright (c) 2002-2005 VIA Technologies Incorporated. Printed in the United States. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. Trademark Notices: is a registered trademark of VIA Technologies, Incorporated. VT6202, VT6212 and VT6212L may only be used to identify products of VIA Technologies, Incorporated. Windows XPTM, Windows 2000TM, Windows METM and Windows 98SETM are registered trademarks of Microsoft Corporation. PCITM is a registered trademark of the PCI Special Interest Group. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices: USA Office: 940 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 -or- (510) 687-4654 Web: http://www.viatech.com Taipei Office: st 1 Floor, No. 531 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 Web: http://www.via.com.tw www..com VT6212 / VT6212L PCI USB2.0 Controller REVISION HISTORY Document Release 1.0 1.01 Date 6/5/03 2/27/04 Revision Initial external release Updated cover page Updated copyright page Changed pins 104, 103, 57, 58, 59, 97 to NC Updated pin-out diagram Updated pin list Updated pin descriptions Added figure 4, lead-free mechanical specification diagram Specified PCI 2.2 bus support Registers updated f0rx41[4], f0rx42[1-0], f0rx48[5], f0rx4B[0], f2rx41[4], f2rx48[5], f2rx49[7-5], f2rx4A, f2rx4B[5, 3-0], f2rx51 Modified legal page Changed pins 60, 63, 64 and 102 to NC Updated pin-out diagram Updated pin list Updated pin descriptions Updated pin information Initials EY JW 1.02 1.03 1.04 1.05 10/21/04 12/21/04 4/19/05 11/16/05 JW JW JW SV 1.06 12/7/05 SV Revision 1.06, December 7, 2005 -i- Revision History www..com VT6212 / VT6212L PCI USB2.0 Controller TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES .........................................................................................................................................................................III LIST OF TABLES ...........................................................................................................................................................................IV PRODUCT FEATURES ................................................................................................................................................................... 1 OVERVIEW....................................................................................................................................................................................... 2 PINOUTS............................................................................................................................................................................................ 3 PIN DIAGRAM ................................................................................................................................................................................ 3 PIN LIST ......................................................................................................................................................................................... 4 PIN DESCRIPTIONS......................................................................................................................................................................... 5 REGISTERS....................................................................................................................................................................................... 8 REGISTER OVERVIEW ................................................................................................................................................................... 8 REGISTER SUMMARY TABLES....................................................................................................................................................... 8 Function 0-1 UHCI Universal Host Controller Interface ................................................................................................... 8 Function 0-1 UHCI PCI Configuration Header ....................................................................................................................................... 8 Function 0-1 UHCI Device Specific Registers........................................................................................................................................ 8 Function 0-1 USB UHCI I/O Registers................................................................................................................................. 8 Function 2 EHCI Enhanced Host Controller Interface ...................................................................................................... 9 Function 2 EHCI PCI Configuration Header........................................................................................................................................... 9 Function 2 EHCI Device Specific Registers ........................................................................................................................................... 9 Function 2 USB EHCI Memory-Mapped I/O Registers ................................................................................................... 10 EHCI Memory Mapped I/O Capability Registers ................................................................................................................................. 10 EHCI Memory Mapped I/O Operational Registers ............................................................................................................................... 10 REGISTER DESCRIPTIONS............................................................................................................................................................ 11 Function 0-1 UHCI Universal Host Controller Interface ................................................................................................. 11 Function 0-1 Configuration Space Header ............................................................................................................................................ 11 Function 0-1 Device Specific Registers ................................................................................................................................................ 12 Function 2 EHCI Enhanced Host Controller Interface .................................................................................................... 14 Function 2 Configuration Space Header................................................................................................................................................ 14 Function 2 Device-Specific Registers ................................................................................................................................................... 15 Function 2 EHCI Compliant USB Memory-Mapped I/O Registers ...................................................................................................... 16 EHCI Capability Registers .................................................................................................................................................................... 16 EHCI Operational Registers .................................................................................................................................................................. 16 ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 17 PACKAGE MECHANICAL SPECIFICATIONS........................................................................................................................ 19 Revision 1.06, December 7, 2005 -ii- Table of Contents www..com VT6212 / VT6212L PCI USB2.0 Controller LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. VT6212 / VT6212L CHIP BLOCK DIAGRAM........................................................................................................ 2 VT6212 (PQFP) / VT6212L (LQFP) PIN DIAGRAM (TOP VIEW) ...................................................................... 3 MECHANICAL SPECIFICATIONS - 128 PIN PQFP (VT6212) / LQFP (VT6212L) PACKAGE .................. 19 LEAD-FREE MECHANICAL SPECIFICATIONS - 128 PIN PQFP (VT6212) / LQFP (VT6212L) PACKAGE .................................................................................................................................................................. 20 Revision 1.06, December 7, 2005 -iii- List of Figures www..com VT6212 / VT6212L PCI USB2.0 Controller LIST OF TABLES TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. VT6212 / VT6212L PIN LIST (ALPHABETICAL ORDER) .................................................................................... 4 VT6212 / VT6212L PIN DESCRIPTIONS .................................................................................................................. 5 ABSOLUTE MAXIMUM RATINGS......................................................................................................................... 17 DC CHARACTERISTICS .......................................................................................................................................... 17 POWER SPECIFICATIONS ...................................................................................................................................... 18 Revision 1.06, December 7, 2005 -iv- List of Tables www..com VT6212 / VT6212L PCI USB2.0 Controller VT6212 / VT6212L PCI USB 2.0 4-Port Host Controller USB 2.0 UHCI / EHCI Host Controller for the PCI 2.2 Bus PRODUCT FEATURES * USB 2.0 - - - - - - - - - * * * * * * * * Compliant with Universal Serial Bus Specification Revision 2.0 Compliant with Enhanced Host Controller Interface Specification Revision 1.0 Compliant with Universal Host Controller Interface Specification Revision 1.1 PCI multi-function device consists of two UHCI Host Controllers for full/low-speed signaling and one EHCI Host Controller core for high-speed signaling 4 downstream facing ports in the root hub with integrated physical layer transceivers shared by UHCI and EHCI Host Controllers Supports PCI-Bus Power Management Interface Specification release 1.1 Legacy support for all downstream facing ports 4 DMA engines with pipelined control for USB data transfer bandwidth improvement Dynamic clock stop control for power consumption reduction Serial EEPROM Support for Boot Register Update Cardbus Mode Support 2.5V Power Supply with 5V Tolerant Inputs 0.22m, Low Power CMOS Process 128-Pin PQFP (VT6212) and 128-Pin LQFP (VT6212L) Packages Available Schematics and PCB Reference Designs Available System Clock Using 24 MHz Crystal Support for PCI Mobile Design Guide Revision 1.06, December 7, 2005 -1- Product Features www..com VT6212 / VT6212L PCI USB2.0 Controller OVERVIEW The VT6212 / VT6212L USB 2.0 UHCI and EHCI Host Controller for the PCI 2.2 Bus provides higher bandwidth (480 Mbps) and is backward compatible with USB 1.1. It implements Universal Serial Bus Specification Revision 2.0 and is compliant with UHCI 1.1 and EHCI 1.0 with a 32-bit PCI host bus interface. The VT6212 / VT6212L adopts 4 DMA engines with pipelined control for USB data transfer bandwidth improvement and dynamic clock stop control for power consumption reduction. The VT6212 / VT6212L supports 4 downstream facing ports with 1.5 (low-speed), 12 (full-speed) and 480 (high-speed) Mbps transaction capability. The Root Hub is integrated with physical-layer transceivers shared by UHCI (for full/low-speed) and EHCI (for high-speed) Host Controllers. The VT6212 / VT6212L also supports PCI-Bus Power Management Interface Specification 1.1 and has legacy support for all downstream facing ports. The VT6212 / VT6212L is ready to provide a PCI 4-port USB2.0 peripheral-interface to satisfy the needs of desktops, mobile systems, and other host platforms. Support for the VT6212 / VT6212L is built into Microsoft Windows XP and Windows 2000. Win98SE and WinME drivers are provided by VIA. PCI Bus INTA# SMI# INTB# PME# INTC# PCI Bus Interface WakeUp_Event WakeUp_Event WakeUp_Event Arbiter UHCI Host Controller #1 UHCI Host Controller #2 EHCI Host Controller Root Hub USB Port 1 USB Port 2 PHY USB Port 3 USB Port 4 Figure 1. VT6212 / VT6212L Chip Block Diagram Revision 1.06, December 7, 2005 -2- Overview Pin Diagram www..com NC NC INTA# INTB# INTC# GND PCICLK VCC33 PCIRST# GNT# REQ# GND VCC25 AD31 AD30 AD29 GND VCC33 AD28 AD27 AD26 AD25 AD24 AD23 GND VCC33 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 O O O I I I O IO IO IO IO IO IO IO IO IO - Revision 1.06, December 7, 2005 PINOUTS VT6212 PCI 4-Port USB2 Host Controller PQFP-128 Figure 2. VT6212 (PQFP) / VT6212L (LQFP) Pin Diagram (Top View) -3I I O O O O I IO IO IO IO IO IO IO IO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 TESTMODE ATPG_EN VCC33 GND SMI# NC NC NC EECS EECK GND VCC25 VCC33 GND EEDI EEDO AD0 AD1 AD2 AD3 VCC33 GND AD4 CBE0# AD5 AD6 AD22 AD21 CBE3# VCC25 GND IDSEL AD20 AD19 GND VCC33 AD18 AD17 AD16 AD15 AD14 AD13 GND VCC33 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# GND VCC33 PAR CBE1# AD12 AD11 AD10 AD9 GND VCC33 VCC25 GND AD8 AD7 IO IO IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IO 102 - 101 - 100 IO 99 IO 98 - 97 - 96 O 95 I 94 - 93 - 92 - 91 - 90 - 89 A 88 - 87 IO 86 IO 85 - 84 - 83 IO 82 IO 81 - 80 - 79 IO 78 IO 77 - 76 - 75 IO 74 IO 73 - 72 I 71 - 70 - 69 I 68 O 67 I 66 I 65 TEST2 VCC33 GND TEST3 WAKEUP_EN NC VCCOSC XOUT XIN GNDOSC GNDPLL VCCPLL GNDPLLA VCCPLLA REXT GNDUSB1 USBP1+ USBP1VCCUSB1 GNDUSB2 USBP2+ USBP2VCCUSB2 GNDUSB3 USBP3+ USBP3VCCUSB3 GNDUSB4 USBP4+ USBP4VCCUSB4 USBOC1# VCCSUS GNDSUS USBOC2# PME# USBOC3# USBOC4# VT6212 / VT6212L PCI USB2.0 Controller Pin Diagram www..com VT6212 / VT6212L PCI USB2.0 Controller Pin List Table 1. VT6212 / VT6212L Pin List (Alphabetical Order) Pin 48 47 46 45 42 40 39 38 37 32 31 30 29 16 15 14 13 12 11 8 7 2 1 126 125 124 123 122 121 118 117 116 Typ PU Pin Name IO AD0 IO AD1 IO AD2 IO AD3 IO AD4 IO AD5 IO AD6 IO AD7 IO AD8 IO AD9 IO AD10 IO AD11 IO AD12 IO AD13 IO AD14 IO AD15 IO AD16 IO AD17 IO AD18 IO AD19 IO AD20 IO AD21 IO AD22 IO AD23 IO AD24 IO AD25 IO AD26 IO AD27 IO AD28 IO AD29 IO AD30 IO AD31 Pin 63 41 28 19 3 23 55 56 50 49 104 103 58 97 57 59 20 5 9 17 25 33 36 43 51 54 61 100 108 114 119 127 Typ I IO IO IO IO IO O O O I IO P P P P P P P P P P P P P P P PU Pin Name PD ATPG_EN CBE0# CBE1# CBE2# CBE3# DEVSEL# PD EECK EECS EEDI PU EEDO NC NC NC NC NC NC FRAME# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin 93 92 90 69 87 83 79 75 112 6 105 106 107 21 27 109 111 67 113 88 60 24 102 99 98 64 22 71 68 66 65 85 Typ P P P P P P P P I I O O O IO IO P I O O A O IO IO IO IO I IO I I I I IO PU Pin Name GNDOSC GNDPLL GNDPLLA GNDSUS GNDUSB1 GNDUSB2 GNDUSB3 GNDUSB4 GNT# IDSEL INTA# INTB# INTC# IRDY# PAR PCICLK PCIRST# PME# REQ# REXT SMI# STOP# TEST2 TEST3 WAKEUP_EN PD TESTMODE TRDY# PU USBOC1# PU USBOC2# PU USBOC3# PU USBOC4# USBP1- Pin 86 81 82 77 78 73 74 4 35 53 115 10 18 26 34 44 52 62 101 110 120 128 96 91 89 70 84 80 76 72 94 95 Typ PU Pin Name IO USBP1+ IO USBP2- IO USBP2+ IO USBP3- IO USBP3+ IO USBP4- IO USBP4+ P VCC25 P VCC25 P VCC25 P VCC25 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCCOSC P VCCPLL P VCCPLLA P VCCSUS P VCCUSB1 P VCCUSB2 P VCCUSB3 P VCCUSB4 I XIN O XOUT Revision 1.06, December 7, 2005 -4- Alphabetical-Order Pin List www..com VT6212 / VT6212L PCI USB2.0 Controller Pin Descriptions Table 2. VT6212 / VT6212L Pin Descriptions PCI Interface Signal Name AD[31:0] CBE[3 :0]# PAR IDSEL DEVSEL# Pin # (see pin list) 3, 19, 28, 41 27 6 23 I/O IO IO IO I IO Power Signal Description VCC33 Address and Data. Addresses are passed during the first clock cycle. Data is passed in subsequent cycles. VCC33 Command / Byte Enables. The command for the current cycle is driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are then driven on following clocks. VCC33 Parity. A single parity bit is provided over AD[31:0] and CBE[3:0]# to check that the data has been transferred accurately.. VCC33 Initialization Device Select. Used as a chip select during configuration read and write cycles. VCC33 Device Select. As an output, this signal is asserted to claim PCI transactions through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT6212-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle. VCC33 Cycle Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. VCC33 PCI Stop. Asserted by the target (the VT6212 / VT6212L chip) to request the master (PCI device) to stop the current transaction. VCC33 Initiator Ready. Asserted when the initiator is ready for data transfer. VCC33 Target Ready. Asserted when the target is ready for data transfer. VCC33 PCI Reset. When detected low, an internal hardware reset is performed. PCIRST# assertion or deassertion may be asynchronous to PCICLK, however, it is recommended that deassertion be synchronous to guarantee a clean and bounce free edge. VCC33 PCI Clock. 33 MHz. Used to clock all PCI bus transactions. VCC33 PCI Interrupt A. Asynchronous signal used to request an interrupt. VCC33 PCI Interrupt B. Asynchronous signal used to request an interrupt. VCC33 PCI Interrupt C. Asynchronous signal used to request an interrupt. VCC33 PCI Bus Request. Asserted by the VT6212 / VT6212L to request bus use. VCC33 PCI Bus Grant. Asserted by the bus arbiter to grant permission to the VT6212 / VT6212L for access to the PCI bus for bus master operations. FRAME# STOP# IRDY# TRDY# PCIRST# 20 24 21 22 111 IO IO IO IO I PCICLK INTA# INTB# INTC# REQ# GNT# 109 105 106 107 113 112 I O O O O I Serial EEPROM Interface Signal Name EECS EECK EEDI EEDO Pin # 56 55 50 49 I/O O O O I Power VCC33 VCC33 VCC33 VCC33 Signal Description EEPROM Chip Select. Connect to EEPROM EECS pin. EEPROM Clock. Connect to EEPROM EECK pin. EEPROM Data In. Connect to EEPROM EEDI pin. EEPROM Data Output. Connect to EEPROM EEDO pin. Chipset South Bridge Interface Signal Name SMI# PME# Pin # 60 67 I/O O O Power VCC33 VCCSUS Signal Description System Management Interrupt. Power Management Event Interrupt. Revision 1.06, December 7, 2005 -5- Pin Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller No Connection Signal Name NC Pin # 57-59, 97, 103-104 I/O - Power Signal Description No connection. USB Ports Signal Name USBP1+ USBP1- USBP2+ USBP2- USBP3+ USBP3- USBP4+ USBP4- USBOC1# Pin # 86 85 82 81 78 77 74 73 71 I/O IO IO IO IO IO IO IO IO I Power VCCUSB1 VCCUSB1 VCCUSB2 VCCUSB2 VCCUSB3 VCCUSB3 VCCUSB4 VCCUSB4 VCCSUS Signal Description USB Port 1 Differential Data Plus. Asserted high (> 2.8V) USB Port 1 Differential Data Minus. Asserted low (< 0.3V) USB Port 2 Differential Data Plus. Asserted high (> 2.8V) USB Port 2 Differential Data Minus. Asserted low (< 0.3V) USB Port 3 Differential Data Plus. Asserted high (> 2.8V) USB Port 3 Differential Data Minus. Asserted low (< 0.3V) USB Port 4 Differential Data Plus. Asserted high (> 2.8V) USB Port 4 Differential Data Minus. Asserted low (< 0.3V) USB Over-Current Input Port 1. When the supplied current exceeds 500 mA on a USB port, USBOC# should be asserted. If this input is asserted low, the host controller will disable USB port 1. The port will remain disabled as long as the condition persists. See Design Guide and evaluation board schematics for overcurrent detection scheme. 68 I USBOC2# VCCSUS USB Over-Current Input Port 2. Same as above but for port 2. 66 I USBOC3# VCCSUS USB Over-Current Input Port 3. Same as above but for port 2. 65 I USBOC4# VCCSUS USB Over-Current Input Port 4. Same as above but for port 2. 94 I XIN VCCOSC Crystal Input. May be connected to a 24 MHz parallel resonant fundamental mode crystal (see Design Guide for specific connection details). 95 O XOUT VCCOSC Crystal Output. Must be connected to a 24 MHz parallel resonant fundamental mode crystal (see Design Guide for specific connection details). 88 A REXT VCCPLL External Resistor. Typical 6.12k 1% pull down to analog ground (see Design Guide for specific connection details). Data encoding is NRZI (Non Return to Zero Inverted) so at times the reverse may be true (i.e., the plus pin may be asserted low and the minus pin asserted high.) Test Pins and Reserved Pins Signal Name ATPG_EN TESTMODE TEST2 TEST3 WAKEUP_EN Pin # 63 64 102 99 98 I/O I I IO IO IO Power VCC25 VCC25 VCC25 VCC25 VCC25 Signal Description Automatic Test Program Generator Enable. Do not connect for normal operation. Internal pulldown. Test Mode Enable. Do not connect for normal operation. Internal pulldown. Test Signal 2. Leave unconnected for normal operation. Test Signal 3. Pull down 4.7K-ohm for normal operation. WAKEUP_EN. Enable wakeup function Revision 1.06, December 7, 2005 -6- Pin Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller Power and Ground Signal Name VCC33 VCC25 GND Pin # 10, 18, 26, 34, 44, 52, 62, 101, 110, 120, 128 4, 35, 53, 115 5, 9, 17, 25, 33, 36, 43, 51, 54, 61, 100, 108, 114, 119, 127 70 69 Power Digital I/O Internal Ground Signal Description Digital I/O Power. 3.3V 100mV Internal Logic Power. 2.5V 5% Ground. Connect to primary PCB ground plane. VCCSUS GNDSUS Suspend Suspend VCCUSB[4-1] GNDUSB[4-1] 72, 76, 80, 84 75, 79, 83, 87 USB Ports USB Ports VCCPLL GNDPLL 91 92 PLL PLL VCCPLLA GNDPLLA 89 90 PLL PLL VCCOSC GNDOSC 96 93 OSC OSC Suspend I/O Power. Connect to system 3.3V 5% suspend power for support of wakeup on USB incoming port activity. Suspend I/O Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. USB Port Power. Connect to system 3.3V 5% suspend power for support of wakeup on USB incoming port activity. USB Port 1-4 Analog Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. PLL Digital Power. Connect to quiet 2.5V 5% power source. PLL Digital Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. PLL Analog Power. Connect to quiet 2.5V 5% power source. PLL Analog Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. Oscillator Power. Connect to quiet 2.5V 5% power source. Oscillator Analog Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. Revision 1.06, December 7, 2005 -7- Pin Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller REGISTERS Register Overview Register settings are located in different sections of this document corresponding to "functions". Each section is indicated by the function number and is dedicated to a specific controller function. These are summarized as follows: Function 0: Universal Host Controller Interface #1 (UHCI) Function 1: Universal Host Controller Interface #2 (UHCI) Function 2: Enhanced Host Controller Interface (EHCI) The tables in this section describe the register settings for the UHCI Host Controllers and the EHCI Host Controller. The registers are listed according to their offset values. The tables show the Access Type (Read/Only, Read/Write, and Read/Write/Clear) and power-on default values ("Default). All offset values are shown in hexadecimal unless otherwise indicated. Default values for each register are also indicated in hexadecimal notation. Note: Registers indicated as RW may have some read-only bits that always read back a fixed value (usually 0 if unused); registers assigned as RWC or WC may have some read-only or read-write bits (see individual register descriptions for details). Register Summary Tables Function 0-1 UHCI Universal Host Controller Interface Function 0-1 UHCI PCI Configuration Header Offset 1-0 3-2 5-4 7-6 8 B-9 C D E F 10-13 17-14 18-1F 23-20 24-27 2B-28 2F-2C 30-33 34 35-3B 3C 3D UHCI PCI Configuration Header Vendor ID Device ID Command Status Revision ID Class Code Cache Line Size Latency Timer Header Type BIST -reservedCIS Base Addr (Cardbus Mode Only) -reservedUHCI-Compliant I/O Base Address -reservedCardbus CIS Pointer Subsystem ID / Subsystem Vendor ID -reservedPower Management Capability -reservedInterrupt Line Interrupt Pin PCI: Cardbus: 3E-3F -reservedDefault 1106 3038 0000 0210 60 0C 03 00 00 16 00 00 00 0000 0000 00 0000 0001 00 0000 0053 3038 1106 00 80 00 00 01, 02 01 00 Acc RO RO RW WC RO RO RW RW RO RW - RW - RW - RO RO - RW - RW RW - Function 0-1 UHCI Device Specific Registers UHCI Device Specific Registers Default Acc Miscellaneous Control 1 RW 40 Miscellaneous Control 2 RW 10 Miscellaneous Control 3 03 RW -reserved00 - Reserved (Do Not Program) - - Miscellaneous Control 5 00 RW Miscellaneous Control 6 RW 0B -reserved00 - Miscellaneous Control 8 00 RW -reserved00 - Serial Bus Release Number RW 10 -reserved00 - Power Management Rx49[0]=0: 7E0A 0001 RO Capabilities Rx49[0]=1: FFC2 0001 84 Power Management Capability Status 00, 03 RW 85-BF -reserved00 - C1-C0 Legacy Support RW 2000 C2-FF -reserved00 - Function 0-1 USB UHCI I/O Registers Offset 1-0 3-2 5-4 7-6 B-8 C D-F 11-10 13-12 14-FF UHCI I/O Registers USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start of Frame Modify -reservedPort 1 Status / Control Port 2 Status / Control -reservedDefault Acc Offset 40 41 42 43 44-47 48 49 4A 4B 4C-5F 60 61-7F 83-80 Revision 1.06, December 7, 2005 -8- Register Summary www..com VT6212 / VT6212L PCI USB2.0 Controller Function 2 EHCI Enhanced Host Controller Interface Function 2 EHCI PCI Configuration Header Offset 1-0 3-2 5-4 7-6 8 B-9 C D E F 13-10 17-14 18-2A 2B-28 2F-2C 30-33 34 35-3B 3C 3D 3E-3F EHCI PCI Configuration Header Vendor ID Device ID Command Status Revision ID Class Code Cache Line Size Latency Timer Header Type BIST Memory Mapped IO Base Address CIS Base Addr (Cardbus Mode Only) -reservedCardbus CIS Pointer Sub-system and Sub-sys Vendor ID -reservedPower Management Capability -reservedInterrupt Line Interrupt Pin -reservedDefault 1106 3104 0000 0210 60 0C 03 20 00 16 00 00 0000 0000 0000 0000 00 0000 00AA 3104 1106 00 80 00 00 03 00h Acc RO RO RW RW RO RO RW RW RO RO RW RW - RO RO - RW - RO RO - Function 2 EHCI Device Specific Registers Offset 40 41 42 43 44-47 48 49 4A 4B 50 51 52-59 5B-5A 5C 5D-5F 60 61 63-62 64-67 6B-68 6F-6C 71-70 72 73 77-74 78-7F 83-80 84 85-FF EHCI Device Specific Registers Default Miscellaneous Control 1 00 Miscellaneous Control 2 00 Miscellaneous Control 3 00 -reserved00 Reserved (Do Not Program) - Miscellaneous Control 4 A0 Miscellaneous Control 5 20 MAC Inter-transaction Delay 00 Parameter MAC Turn-around Time Parameter 09 Reserved (Do Not Program) - USB 2.0 Timeout RX Parameter 5A Reserved (Do Not Program) - Hi-Speed Port Pad Termination 4444 Resistor Fine Tune Reserved (Do Not Program) - -reserved00 Serial Bus Release Number Frame Length Adjust Port Wake Capability -reserved00 USB Legacy Support Extd Capability 0000 0001 USB Legacy Support Control / Status 0000 0000 SRAM Direct Access Address 0000 -reserved00 SRAM Direct Access Control 00 SRAM Direct Access Data 0000 0000 -reserved00 Power Management Rx49[1]=0: 7E0A 0001 Capabilities Rx49[1]=1: FFC2 0001 Power Management Capability Status -reserved00 Acc RW RW RW - - RW RW RO RW - RW - RW - - RO RW RW - RW RW RW - RW RW - RO RW - Revision 1.06, December 7, 2005 -9- Register Summary www..com VT6212 / VT6212L PCI USB2.0 Controller Function 2 USB EHCI Memory-Mapped I/O Registers EHCI Memory Mapped I/O Capability Registers Offset 0 1 3-2 7-4 B-8 C-F EHCI Capability Registers Capability Register Length -reservedInterface Version Number Structure Parameters Capability Parameters -reservedDefault 10 00 0100 0000 2204 0000 6872 00 Acc RW - RW RW RW - EHCI Memory Mapped I/O Operational Registers Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 2B-28 2C-4F 53-50 57-54 5B-58 5F-5C 63-60 64-FF EHCI Operational Registers USB Command USB Status USB Interrupt Enable USB Frame Index 4G Segment Selector Frame List Base Address Next Asynchronous List Address Reserved Configured Flag Port 1 Status / Control Port 2 Status / Control Port 3 Status / Control Port 4 Status / Control -reservedDefault Acc Revision 1.06, December 7, 2005 -10- Register Summary www..com VT6212 / VT6212L PCI USB2.0 Controller Offset 7-6 - Status Register (0210h)................................ RW 15 Reserved ........................................always reads 0 14 Signaled System Error.......................always reads 0 13 Received Master Abort ................................... RWC Set by the VT6212 interface logic if it generates a master abort while acting as a master......... default = 0 12 Received Target Abort.................................... RWC Set by the VT6212 interface logic if it receives a target abort while acting as a master .......... default = 0 11 Signaled Target Abort 10-9 DEVSEL# Timing 00 Fast 01 Medium .................................................... fixed 10 Slow 11 Reserved 8-5 Reserved ........................................always reads 0 4 Power Management Interrupt ........ always reads 1 3-0 Reserved ........................................always reads 0 Offset 8 - Revision ID (60h) .............................................. RO Offset B-9 - Class Code (0C 03 00h)................................. RO 23-0 Class Code fixed value indicates USB 1.1 Controller Offset C - Cache Line Size (00h) ..................................... RW Offset D - Latency Timer (16h) ....................................... RW Offset E - Header Type (00h)............................................ RO Offset F - BIST (00h) ......................................................... RO Offset 17-14 - CIS Base Addr - Cardbus Mode Only ... RW 31-8 Correspond to AD [31:8] ......................... default = 0 7-0 Reserved ........................................always reads 0 Offset 23-20 - Base Address for UHCI 1.1 Compliant USB I/O ...................................................................................... RW 31-16 Reserved ........................................always reads 0 15-5 Port Base Address for USB IO Registers Corresponding to AD[15:5]...................................... 4-0 Fixed ..............................always reads 00001b Offset 31-8 7-3 2-0 2B-28 - Cardbus CIS Pointer .............................. RO Reserved ........................................always reads 0 Cardbus CIS Pointer ............................. fixed at 50h Second Base Address ........................fixed at 3'b010 Register Descriptions Function 0-1 UHCI Universal Host Controller Interface The VT6212 / VT6212L contains two USB host controllers, which are controlled by functions 0 and 1 respectively. Register definitions for both controllers are identical, except where noted. Function 0 and function 1 registers conform to the UHCI (Universal Host Controller Interface) Specification. There are two sets of registers: PCI configuration space registers (located in functions 0 and 1) and USB I/O registers (located in system I/O space at offsets from the address stored in the Base Address Register). Function 0-1 Configuration Space Header Offset 1-0 - Vendor ID (1106h) .........................................RO 15-0 Vendor ID ....................1106h = VIA Technologies Offset 3-2 - Device ID (3038h) ...........................................RO 15-0 Device ID .......reads 3038h to identify the VT6212 Offset 5-4 - Command Register (0000h).........................RW 15-8 Reserved ........................................ always reads 0 7 Address Stepping 0 Disable ...................................................default 1 Enable 6-5 Reserved ........................................ always reads 0 4 Memory Write and Invalidate 0 Disable ...................................................default 1 Enable 3 Special Cycle ...............................................fixed at 0 2 Bus Master 0 Disable ...................................................default 1 Enable 1 Memory Space 0 Disable ...................................................default 1 Enable 0 I/O Space 0 Disable ...................................................default 1 Enable Offset 2F-2C - Subsystem ID / Subsystem Vendor ID.. RO 24-0 Subsystem ID / Subsystem Vendor ID Rx42[4] = 0 ................................ fixed at 30381106h Offset 34 - Power Management Capability (80h) .......... RO Offset 3C - Interrupt Line (00h)....................................... RO Offset 3D - Interrupt Pin (01h, 02h)................................. RO Revision 1.06, December 7, 2005 -11- Function 0-1 Register Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller Offset 42 - Miscellaneous Control 3 (03h) ...................... RW 7-2 Reserved (Do Not Program).................... default = 0 1-0 Release continuous REQ_ after N PCICLKs (feature controlled by Function 0's register) 00 Do not release 01~11 Number X 32 PCICLKs Function 0-1 Device Specific Registers Offset 40 - Miscellaneous Control 1 (40h).......................RW 7 PCI Memory Command Option 0 Support "Memory Read Line", "Memory Read Multiple", and "Memory Write and Invalidate" commands............................default 1 Support only "Memory Read" and "Memory Write" commands 6 Babble Option 0 Auto-disable babbled port on EOF 1 Keep babbled port enabled.....................default 5 PCI Parity Check 0 Disable ...................................................default 1 Enable 4 Reserved (Do Not Program) ................... default = 0 3 USB Data Length Option 0 Support transmit data length up to 1280 ......def 1 Support transmit data length up to 1023 2 Improve FIFO Latency for packets less than 64B 0 Enable ....................................................default 1 Disable 1 DMA Options 0 8DW burst access with better FIFO latency def 1 16DW burst access (original performance level) 0 PCI Wait State 0 Zero Wait States.....................................default 1 One Wait State Offset 48 - Miscellaneous Control 5 (00h) ...................... RW 7-6 Reserved (Do Not Program).................... default = 0 5 Enable enhanced PCI read command generation in reading descriptors 0 Enable.......................................................... def 1 Disable 4-0 Reserved (Do Not Program).................... default = 0 Offset 49 - Miscellaneous Control 6 (0Bh)...................... RW 7-2 Reserved (Do Not Program).................... default = 0 1 EHCI Supports PME# Assertion in D3cold State 0 Not support 1 Supported .............................................. default 0 UHCI Supports PME# Assertion in D3cold State 0 No Support 1 Supported .............................................. default Offset 41 - Miscellaneous Control 2 (10h).......................RW 7-5 Reserved (Do Not Program) ................... default = 0 4 Hold PCI REQ_ for successive access 0 Disable 1 Enable 3 Reserved (Do Not Program) ................... default = 0 2 Trap Option 0 Set trap 60/64 status bits without checking enable bits ..............................................default 1 Set trap 60/64 status bits only when trap 60/64 enable bits are set 1 A20Gate Pass Through Option 0 Pass through A20Gate command sequence .def 1 Do not pass through write I/O port 64 0 Reserved (Do Not Program) ................... default = 0 Offset 4B - Miscellaneous Control 8 (00h)...................... RW 7-1 Reserved .............................................. default = 0 0 Cardbus mode select (strapped via EESK) 0 PCI mode 1 Cardbus mode Offset 60 - Serial Bus Release Number (10h) .................. RO Offset 83-80 - Power Management Capabilities ............. RO 24-0 Power Management Capabilities Rx49[0] = 0 ............................. fixed at 00 02 00 01h Rx49[0] = 1 ............................fixed at C9 C2 00 01h Offset 84 - Power Mgmt Capability Status (00h or 03h) RW Offset C1-C0 - UHCI 1.1 Legacy Support (2000h)........ RW Function 0-1 UHCI Compliant USB I/O Registers The USB I/O registers are compliant with the UHCI v1.1 standard. For more details of the register configurations, refer to the relevant documentation for the UHCI V1.1 standard. Revision 1.06, December 7, 2005 -12- Function 0-1 Register Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start of Frame Modify I/O Offset 11-10 - Port 1 Status / Control I/O Offset 13-12 - Port 2 Status / Control Revision 1.06, December 7, 2005 -13- Function 0-1 Register Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller Offset 7-6 - Status (0210h)............................................... RW 15 Reserved ........................................always reads 0 14 Signaled System Error............................. default = 0 13 Received Master Abort ............................ default = 0 12 Received Target Abort............................. default = 0 11 Signaled Target Abort ............................. default = 0 10-9 DEVS EL# Timing 00 Fast 01 Medium .................................................... fixed 10 Slow 11 Reserved 8-5 Reserved ........................................always reads 0 4 Power Management Interrupt ........ always reads 1 3-0 Reserved ........................................always reads 0 Offset 8 - Revision ID (60h) .............................................. RO Offset B-9 - Class Code (0C0320=EHCI Host Controller) RO 23-0 Fixed value of class code indicates USB2.0 EHCI Host Controller Offset C - Cache Line Size (00h) ..................................... RW Offset D - Latency Timer: (16h)...................................... RW Function 2 EHCI Enhanced Host Controller Interface In addition to the UHCI host controllers at functions 0 and 1, the VT6212 / VT6212L also contains another USB host controller, which conforms to the EHCI (Enhanced Host Controller Interface) Specification. There are two sets of registers: PCI configuration space registers (located in function 2) and USB Memory Mapped I/O registers, (located in system memory at offsets from the address stored in the Base Address Register). Function 2 Configuration Space Header Offset 1-0 - Vendor ID (1106h) ........................................ RO 7-0 Vendor ID ....................1106h = VIA Technologies Offset 3-2 - Device ID (3104h) ...........................................RO 7-0 Device ID ........................3104h = EHCI controller Offset 5-4 - Command (0000h) ........................................RW 15-8 Reserved ............................................. always reads 0 7 Address Stepping 0 Disable ...................................................default 1 Enable 6-5 Reserved ................................fixed at 0 (disabled) 4 Memory Write and Invalidate 0 Disable ...................................................default 1 Enable 3 Special Cycle ...............................................fixed at 0 2 Bus Master 0 Disable ...................................................default 1 Enable 1 Memory Space 0 Disable ...................................................default 1 Enable 0 I/O Space 0 Disable ...................................................default 1 Enable Offset E - Header Type (00h)............................................ RO Offset F - BIST (00h) ......................................................... RO Offset 13-10 - EHCI 0.95 Memory Mapped I/O Base .. RW 31-8 I/O Base Address for EHCI 0.95 USB Memory Mapped I/O Registers .............................. default = 0 (these bits correspond to AD[31:8]) 7-3 Reserved..............................................always reads 0 2-1 Fixed .....fixed at 00h (32-bit addressing only) 0 Reserved..............................................always reads 0 Offset 17-14 - CIS Base Addr - Cardbus Mode Only ... RW 31-8 Correspond to AD [31:8] ......................... default = 0 7-0 Reserved ........................................always reads 0 Offset 31-8 7-3 2-0 2B-28 - Cardbus CIS Pointer (AAh) ................... RO Reserved ........................................always reads 0 Cardbus CIS Pointer ............................ fixed at A8h Second Base Address ........................fixed at 3'b010 Offset 34 - Power Management Capability (80h)........... RO Offset 3C - Interrupt Line (00h)....................................... RO Offset 3D - Interrupt Pin (03h)......................................... RO Revision 1.06, December 7, 2005 -14- Function 2 Register Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller Offset 49 - Miscellaneous Control 5 (20h) ...................... RW 7 Enable MAC (provides more delay between transactions) 0 Disable................................................... default 1 Enable 6 Enable MAC (provides timeout to device when error is detected) 0 Disable................................................... default 1 Enable 5 Clock Auto Stop 0 Disable, no stop 1 Enable, auto stop ................................... default 4-0 Reserved ........................................always reads 0 Offset 4A - MAC inter-transaction delay parameter (00h)RO Offset 4B - MAC turn around time parameter (09h).... RW 7-6 Reserved ........................................always reads 0 5 EHCI sleep time select 0 1 s .................................................... default 1 10 s 4 Reserved ........................................always reads 0 3-0 USB 2.0 MAC TX time parameter ......... default = 9 Offset 51 - USB 2.0 Timeout RX Parameter (5Ah) ....... RW Offset 5B 5A - High-Speed Port Pad Termination Resistor Fine Tune (4444h)............................................................. RW 15-12 Control A[3:0] ........................................ default = 4h 11-8 Control B[3:0]......................................... default = 4h 7-4 Control C[3:0] ........................................ default = 4h 3-0 Control D[3:0] ........................................ default = 4h Offset 60 - Serial Bus Number (20h = USB 2.0) .............. RO Offset 61- Frame Length Adjust (20h) ........................... RW Offset 63-62 - Port Wake Capability (0001h)................. RW Offset 83-80 - Power Management Capability................ RO Function 0 49[1] = 0: ............................fixed at C9 C2 00 01h Function 0 49[1] = 1: ............................ fixed at 48 0A 00 01h Offset 84 - Power Mgmt Capability Status (00h or 03h) RW Function 2 Device-Specific Registers Offset 40 - Miscellaneous Control 1 (00h).......................RW 7 PCI Memory Command Option 0 Support "Memory Read Line", "Memory Read Multiple", and "Memory Write and Invalidate" commands............................default 1 Only supports "Memory Read" and "Memory Write" commands 6 Babble Option 0 Auto-disable babbled port when EOF ...default 1 Keep babbled port enabled 5 PCI Parity Check 0 Disable ...................................................default 1 Enable 4 Reserved (Do Not Program) ................... default = 0 3-2 Reserved ........................................ always reads 0 1 DMA Options 0 8DW burst access...................................default 1 16DW burst access 0 PCI Wait States 0 Zero Wait States.....................................default 1 One Wait State Offset 41 - Miscellaneous Control 2 (00h).......................RW 7-5 Reserved ........................................ always reads 0 4 Hold PCI REQ_ for successive access 0 Disable 1 Enable 3-0 Reserved ........................................ always reads 0 Offset 42 - Miscellaneous Control 3 (00h).......................RW 7-5 Reserved ........................................ always reads 0 4 Sub-system and sub-system Vendor ID R/W 0 Disable ...................................................default 1 Enable 3-0 Reserved ........................................ always reads 0 Offset 48 - Miscellaneous Control 4 (A0h) ......................RW 7-6 Reserved ........................................ always reads 0 5 Disable PCI burst access 0 Burst enable ...........................................default 1 Burst disable 4-0 Reserved ........................................ always reads 0 Revision 1.06, December 7, 2005 -15- Function 2 Register Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller Function 2 EHCI Compliant USB Memory-Mapped I/O Registers The USB Memory Mapped I/O registers are compliant with the EHCI standard. For more details of the register configurations, refer to the relevant documentation for the EHCI standard. EHCI Capability Registers Offset 0 - Capability Register Length (10h)....................RW Offset 3-2 - Interface Version Number (0100h)..............RW Offset 7-4 - Structure Parameters (00002204h)..............RW Offset B-8 - Capability Parameters (00006872h) ...........RW EHCI Operational Registers Offset 13-10 - USB Command..........................................RW Offset 17-14 - USB Status .................................................RW Offset 1B-18 - USB Interrupt Enable..............................RW Offset 1F-1C - USB Frame Index ....................................RW Offset 23-20 - 4G Segment Select.....................................RW Offset 27-24 - Frame List Base Address..........................RW Offset 2B-28 - Next Asynchronous List Address............RW Offset 53-50 - Configured Flag ........................................RW Offset 57-54 - Port 1 Status / Control..............................RW Offset 5B-58 - Port 2 Status / Control .............................RW Offset 5F-5C - Port 3 Status / Control ............................RW Offset 63-60 - Port 4 Status / Control..............................RW Revision 1.06, December 7, 2005 -16- Function 2 Register Descriptions www..com VT6212 / VT6212L PCI USB2.0 Controller ELECTRICAL SPECIFICATIONS Table 3. Absolute Maximum Ratings Symbol Parameter TSTG TC VCC VI VO VESD Storage temperature Case operating temperature Power supply voltages Input voltage Output voltage at any output Electrostatic discharge Min -55 0 -0.5 -0.5 -0.5 Max 125 85 4.0 5.5 VCC + 0.5 2 Unit oC oC V V V kV Comment Human Body Model Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions. Table 4. DC Characteristics TC = 0-55oC, VCCPCI = VCCSUS = VCCUSBN = 3.3V+/-5%, VCC25 = VCCOSC = VCCPLL = VCCPLLA =2.5V+/-5%, GND = 0V Symbol Parameter VIL VIH VOL VOH IIL IOZ Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Tristate Leakage Current Min -0.50 2.0 2.4 - Max 0.8 VCC+0.5 0.45 +/-10 +/-20 Unit V V V V A A Condition IOL=4.0mA IOH=-1.0mA 0 -17- Electrical Specifications www..com VT6212 / VT6212L PCI USB2.0 Controller Table 5. Power Specifications TC = 0-55oC, VCC33 = VCCSUS = VCCUSB = 3.3V+/-5%, VCC25 = VCCOSC = VCCPLL = VCCPLLA =2.5V+/-5%, GND = 0V Symbol ICC25-PD ICC33-PD ICC25 ICC33 ICC25A ICC0USB ICC1USB ICC2USB ICC3USB ICC4USB PD-PD PD-IDLE PD-4USB Parameter Power Supply Current - 2.5V Power Supply Current - 3.3V Power Supply Current - VCC25 (2.5V) Power Supply Current - VCC33 (3.3V) Power Supply Current - Analog (2.5V) Power Supply Current - USB (3.3V) Power Supply Current - USB (3.3V) Power Supply Current - USB (3.3V) Power Supply Current - USB (3.3V) Power Supply Current - USB (3.3V) Overall Chip Power Dissipation Overall Chip Power Dissipation Overall Chip Power Dissipation Typ 1.1 5.4 38 89 60 47 105 160 211 263 18 672 1312 Max Unit mA mA mA mA mA mA mA mA mA mA mW mW mW Condition Power down or suspend Power down or suspend Idle with no port activity Idle with no port activity Idle with no port activity Idle with no port activity One port transmitting Two ports transmitting Three ports transmitting Four ports transmitting Power down or suspend Idle with no port activity Four ports transmitting "Analog 2.5V" power includes VCCPLL, VCCPLLA, and VCCOSC "USB 3.3V" power includes VCCUSB and VCCSUS Revision 1.06, December 7, 2005 -18- Electrical Specifications www..com VT6212 / VT6212L PCI USB2.0 Controller PACKAGE MECHANICAL SPECIFICATIONS PQFP = 23.2 +/-0.2, LQFP = 22.0 +/-0.2 20.0 +/-0.2 102 103 65 0.75TYP 64 Chip Part number PQFP Package = VT6212 LQFP Package = VT6212L VT6212 YYWWVV TAIWAN CM LLLLLLLLLL 39 1 0.5 0.2 +/-0.03 38 0.08 Y W V L = Date Code Year = Date Code Week = Chip Version = Lot Code 128 0.75TYP M PQFP = 3.40 Max LQFP = 1.60 Max 0.1 PQFP = 23.2+/-0.2, LQFP = 22.0+/-0.2 PQFP = 2.70 +/-0.20 LQFP = 1.40 +/-0.05 PQFP = 0.25 Min LQFP = 0.05 Min 0.15 Max +0.1 0.15 -0.05 0~10 o PQFP = 0.5+/-0.2 LQFP = 0.6+/-0.15 Figure 3. Mechanical Specifications - 128 Pin PQFP (VT6212) / LQFP (VT6212L) Package Revision 1.06, December 7, 2005 -19- Mechanical Specifications PQFP = 17.2 +/-0.2, LQFP = 16.0 +/-0.2 14.0 +/-0.2 www..com VT6212 / VT6212L PCI USB2.0 Controller PQFP = 23.2 +/-0.2, LQFP = 22.0 +/-0.2 20.0 +/-0.2 102 103 65 0.75TYP 64 Chip Part number PQFP Package = VT6212 LQFP Package = VT6212L VT6212 YYWWVV TAIWAN CMG LLLLLLLLLL 39 1 0.5 0.2 +/-0.03 38 0.08 Y W V L = Date Code Year = Date Code Week = Chip Version = Lot Code 128 0.75TYP M Indicates Lead-Free Package PQFP = 3.40 Max LQFP = 1.60 Max 0.1 PQFP = 23.2+/-0.2, LQFP = 22.0+/-0.2 PQFP = 2.70 +/-0.20 LQFP = 1.40 +/-0.05 PQFP = 0.25 Min LQFP = 0.05 Min 0.15 Max +0.1 0.15 -0.05 0~10 o PQFP = 0.5+/-0.2 LQFP = 0.6+/-0.15 Figure 4. Lead-free Mechanical Specifications - 128 Pin PQFP (VT6212) / LQFP (VT6212L) Package Revision 1.06, December 7, 2005 -20- Mechanical Specifications PQFP = 17.2 +/-0.2, LQFP = 16.0 +/-0.2 14.0 +/-0.2 |
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